Posts on HyperAccel Tech Blog

[Exploring torch.compile() - Part 03] Three Keywords from PyTorch Conference 2026: Agent, Acceleration, Ecosystem

contact@hyperaccel.ai (HyperAccel) — Fri, 06 Nov 2026 15:48:45 +0900

A PyTorch Conference 2026 report. It covers CI and refactoring to validate a growing volume of contributions, torch.compile improvements such as the C++ FakeTensor, inference optimization in vLLM, and how NPU companies including Huawei Ascend and IBM Spyre build tools to join the PyTorch ecosystem.

[Ceph Deep-Dive - Part 01] CRUSH

contact@hyperaccel.ai (HyperAccel) — Tue, 03 Nov 2026 13:18:45 +0900

Ceph is one of the most widely used open-source distributed storage systems. Let's take it apart, starting from its foundation: the CRUSH algorithm.

Verifying an LLM Inference Chip, Part 1: Where Does the Ground Truth Come From?

contact@hyperaccel.ai (HyperAccel) — Wed, 21 Oct 2026 10:35:01 +0900

Where does the ground truth come from in LLM inference chip verification? We explain why the IP level treats the spec document as ground truth, why the top level uses the AI model's output, and what each comparison in between catches.

Monads and Category Theory ② Different Computations, the Same Composition

contact@hyperaccel.ai (HyperAccel) — Mon, 19 Oct 2026 12:51:34 +0900

What laws let us group and recombine computations? We examine the composition we built as a mathematical category.

[Exploring torch.compile() - Part 02] Why Split It into Three Stages?

contact@hyperaccel.ai (HyperAccel) — Fri, 16 Oct 2026 18:00:00 +0900

An ecosystem view of why torch.compile is split into three stages. We trace how PyTorch drew people in by being as easy to use as plain Python and how it has opened up since 2.0, then look at how compiler backends like TensorRT, OpenVINO, and XLA, torch.export, GPUs, and new AI chips each use the outputs of the Dynamo, AOTAutograd, and Inductor stages. Huawei Ascend, Intel Gaudi, and IBM Spyre are compared along the way.

[Monads and Category Theory - Part 01] When Functions Do Not Compose

contact@hyperaccel.ai (HyperAccel) — Fri, 25 Sep 2026 09:00:00 +0900

Connect computations that may produce no value and build a first composition rule on the way to understanding monads.

[Know Your Enemy - Part 07] A Model Trained on GPUs Builds a Better Chip Than GPUs

contact@hyperaccel.ai (HyperAccel) — Tue, 08 Sep 2026 09:42:25 +0900

The era of using AI to build chips that run AI has arrived. Drawing on publicly released information about Jalapeño, OpenAI’s custom chip, this article explores what that means.

[Memory in the AI Era - Part 05] Exploring CXL Workloads

contact@hyperaccel.ai (HyperAccel) — Wed, 12 Aug 2026 17:39:35 +0900

We examine how CXL is used in real workloads through KV cache offload, memory pooling, and memory tiering.

[Exploring torch.compile() - Part 01] The Three Components

contact@hyperaccel.ai (HyperAccel) — Tue, 04 Aug 2026 18:00:00 +0900

A walkthrough of the three components behind torch.compile: TorchDynamo, AOTAutograd, and TorchInductor. Covers what a graph is, bytecode interception and guards, graph breaks, operator normalization below the dispatcher, and per-element IR with code generation.

[Know Your Enemy - Part 06] The Agentic AI Era — The Revival of the CPU and the Dawn of the CPU Three Kingdoms

contact@hyperaccel.ai (HyperAccel) — Thu, 02 Jul 2026 14:33:50 +0900

We analyze why the CPU became the bottleneck of inference infrastructure in Agentic AI workloads, walk through the latest datacenter CPU lineups from the three CPU vendors, and explore why the CPU has risen to prominence again in the Agentic AI era.

[Legato - Part 01] A Programming Language for HyperAccel LPU

contact@hyperaccel.ai (HyperAccel) — Sun, 28 Jun 2026 16:17:48 +0900

An introduction to Legato — HyperAccel’s programming model and compiler stack for the LPU — covering what it is, why it exists, and how it is designed.

[AI Agent - Part 02] Back to the Terminal: How Agents Made Remote Development Feel Native

contact@hyperaccel.ai (HyperAccel) — Tue, 16 Jun 2026 10:00:00 +0900

AI coding agents did not just change how we write code. They changed where work can happen: over SSH, inside Termux, in Kubernetes pods, and from remote machines that no longer need a full local editor setup.

[Memory in the AI Era - Part 04] Understanding CXL

contact@hyperaccel.ai (HyperAccel) — Thu, 04 Jun 2026 10:12:00 +0900

We analyze the background behind CXL (Compute Express Link), its three sub-protocols (CXL.io/.cache/.mem), the Type 1/2/3 device classification, the standard's evolution from 1.1 to 3.x, and the CXL memory product lineups of Samsung, SK hynix, and Micron.

[Memory in the AI Era - Part 03] The Remaining Challenges of HBF

contact@hyperaccel.ai (HyperAccel) — Thu, 28 May 2026 13:42:34 +0900

HBF clearly has its place, but it still has gaps to fill before it can claim a spot in the memory hierarchy pyramid. We walk through the latest LLM model and inference workload trends, how Flash memory is actually used in LLM serving today, and the remaining challenges HBF has to solve.

[Memory in the AI Era - Part 02] Where Does HBF Actually Fit?

contact@hyperaccel.ai (HyperAccel) — Wed, 29 Apr 2026 02:00:00 +0900

Centered on SK hynix's H³ architecture, we explore workloads that can overcome HBF's weaknesses.

[Know Your Enemy - Part 05] Cerebras and the Wafer-Scale Engine

contact@hyperaccel.ai (HyperAccel) — Mon, 27 Apr 2026 10:00:00 +0900

This post explains Cerebras's recent momentum, WSE-3 architecture, and the trade-offs of wafer-scale chips in a beginner-friendly way, following reports of a large OpenAI deal.

[Memory in the AI Era - Part 01] Understanding HBF

contact@hyperaccel.ai (HyperAccel) — Thu, 23 Apr 2026 12:34:00 +0900

We explain the cell structures and physical characteristics of SRAM, DRAM, HBM, and NAND, and analyze how High Bandwidth Flash (HBF) fills the gap in the memory hierarchy.

Project Glasswing: Claude Mythos Preview

contact@hyperaccel.ai (HyperAccel) — Fri, 17 Apr 2026 10:00:00 +0900

What Glasswing and Mythos Preview signal, quantitative gaps vs. Opus 4.6, benchmark generation shift, OpenBSD/FFmpeg/FreeBSD cases, and takeaways for defenders and developers.

[K8s Dev Environment - Part 03] Kubernetes Device Plugin for LPU

contact@hyperaccel.ai (HyperAccel) — Fri, 27 Mar 2026 10:38:13 +0900

Hello! I’m Younghoon Jun, a DevOps Engineer on the ML team at HyperAccel.

This post is the third installment of the Building an In-House Dev Environment on Kubernetes series!

In Part 1, we covered the background, overall design, and direction of building a Kubernetes-based development environment. Part 2 introduced the strategy and process for building an ARC-based CI/CD infrastructure to overcome the structural limitations of self-hosted runners. In this third article, we will discuss the Device Plugin required for utilizing custom resources on Kubernetes.

AITER Analysis: How AMD Doubled ROCm Inference Performance

contact@hyperaccel.ai (HyperAccel) — Tue, 17 Mar 2026 10:00:00 +0900

An analysis of AMD's AITER kernel library that doubled ROCm inference performance. We examine its four kernel backend strategies (Triton, CK, HIP, ASM), JIT compile pipeline, and the architecture that achieved ~2× throughput improvement on DeepSeek R1.

Transformer World: A Deep Dive into the Building Blocks of LLMs

contact@hyperaccel.ai (HyperAccel) — Thu, 05 Mar 2026 10:00:00 +0900

A step-by-step walkthrough of Transformer-based LLM internals: the role of Token Embedding, Attention, LM Head, and optimization techniques such as KV Cache, MHA, and GQA.

[Know Your Enemy - Extra] Pallas Programming Model

contact@hyperaccel.ai (HyperAccel) — Wed, 25 Feb 2026 14:50:09 +0900

Building on the TPU architecture explored in part 2, we examine Pallas, a programming model that enables writing custom kernels on TPU.

[Know Your Enemy - Part 04] Memory Capacity Bottleneck and NVIDIA ICMS

contact@hyperaccel.ai (HyperAccel) — Tue, 24 Feb 2026 21:04:00 +0900

We explore the technical principles behind NVIDIA's ICMS — a new storage tier designed to solve the KV cache capacity bottleneck in LLMs — and the Bluefield-4 DPU that manages it.

[AI Agent - Part 01] From Copy-Paste to Autonomous Agents: A Subtle Introduction

contact@hyperaccel.ai (HyperAccel) — Thu, 19 Feb 2026 14:16:19 +0900

Hello, my name is Taeseo Um, currently on the ML team at HyperAccel.

There is a running joke among developers that our job has always been about googling the issue, clicking the first link that pops up, then copying from Stack Overflow. In some ways, the arrival of AI coding tools didn’t change what we do — it just made us dramatically better at it. Over the past few months, our team has ridden almost every wave of AI-assisted development, from the earliest interactions to the autonomous agents we rely on today. Here’s what that journey looked like, what we learned, and where we think it’s all heading.

[K8s Dev Environment - Part 02] CI/CD Infrastructure Modernization with ARC

contact@hyperaccel.ai (HyperAccel) — Thu, 12 Feb 2026 09:30:00 +0900

The complete journey of redesigning HyperAccel’s CI/CD infrastructure based on Actions Runner Controller (ARC), including Vault JWT/Kubernetes Auth dual integration, and achieving pipeline observability through a custom-built Go-based Prometheus Exporter.

[K8s Dev Environment - Part 01] Why Kubernetes?

contact@hyperaccel.ai (HyperAccel) — Mon, 09 Feb 2026 10:38:13 +0900

Hello! I’m Younghoon Jun, a DevOps Engineer on the ML team at HyperAccel.

For those of you reading this, what kind of environment do you develop in? I imagine you’re working in various environments—local setups, SSH server access, cloud services, and more.

HyperAccel develops on an environment built on top of a Kubernetes cluster. We spin up Pods based on devcontainers pre-configured with the packages needed for development, then connect to the container to do our work. To make things easier for our internal developers, we’ve created and provided a Devcontainer Portal.

[Know Your Enemy - Part 03] Groq's LPU (Acquired by NVIDIA for $20B)

contact@hyperaccel.ai (HyperAccel) — Tue, 03 Feb 2026 11:24:57 +0900

We explore the background of Groq and LPU, their hardware/software design philosophy, and analyze NVIDIA's intentions behind acquiring Groq.

Specs are All You Need: What is Spec-Driven Development (SDD)?

contact@hyperaccel.ai (HyperAccel) — Tue, 03 Feb 2026 10:17:33 +0900

Spec-Driven Development (SDD) is a new development methodology for the AI era, moving beyond prompt engineering to spec engineering.

[Crafting Compilers - Part 03] Polyhedral Analysis

contact@hyperaccel.ai (HyperAccel) — Thu, 29 Jan 2026 15:10:28 +0900

A concise walk-through of polyhedral compiler basics, covering affine concepts, polyhedra and Farkas lemma, iteration/schedule vectors, parallelism analysis, and polyhedral transformation.

CES 2026 Key Highlights from a 2025 Participant (feat. SAMSUNG, SK, LG)

contact@hyperaccel.ai (HyperAccel) — Mon, 12 Jan 2026 10:00:00 +0900

CES 2026 Key Highlights from a 2025 Participant (feat. SAMSUNG, SK, LG)

Hello! I’m Hyunjun Park from the HyperAccel ML Team.

CES, which started in Las Vegas on January 6th, successfully concluded on January 9th. I participated in last year’s (2025) CES and operated the HyperAccel booth, and based on that experience, I’d like to review this year’s (2026) CES. Some might wonder why I’m posting this now instead of last year.

[Know Your Enemy - Part 02] TPU Emergence and Rise

contact@hyperaccel.ai (HyperAccel) — Sat, 03 Jan 2026 17:20:16 +0900

We explore the background of Google's AI chip TPU, born in 2016, and analyze Google's AI semiconductor market strategy to compete with NVIDIA by examining the hardware and software architecture built over 10 years.

[Know Your Enemy - Part 01] GPU History and Fundamentals

contact@hyperaccel.ai (HyperAccel) — Mon, 29 Dec 2025 10:54:53 +0900

From 1990s graphics cards through Tesla and CUDA to Hopper, this post walks through the evolution of NVIDIA GPUs and explains how modern GPUs use warps, scheduling and memory hierarchy to hide memory latency and deliver massive parallel performance.

Starting Our Tech Blog

contact@hyperaccel.ai (HyperAccel) — Fri, 26 Dec 2025 10:38:16 +0900

The Motivation Behind Starting Our Tech Blog

In our company’s SW group, we have a developer named Jaewoo Kim (Author, LinkedIn). Jaewoo is developing legato, a language for our HW kernel development. For several months, Jaewoo has been consistently requesting something from us.

Shouldn’t we have a company tech blog? (from Jaewoo)

Jaewoo mentioned that he had experience posting projects from his previous company on a tech blog, and thanks to those posts, many talented developers became interested in the company and even joined.

[Crafting Compilers - Part 02] Building a Programming Language

contact@hyperaccel.ai (HyperAccel) — Sat, 13 Dec 2025 15:10:28 +0900

Before building a compiler, we need to define the language it will compile. A programming language isn’t just syntax and semantics—it’s the user interface between humans and computers.

What Is a Programming Language?

Abstraction is one of the core ideas in computer science. Without abstraction, interacting with computers would require understanding electrical signals, memory layout, registers, and countless hardware details.

A programming language simplifies this complexity. It provides a human-friendly way to express ideas while hiding the low-level mechanisms that make them work. In this sense, a programming language functions as a UI for computing—a layer that lets us focus on building logic, applications, and systems, rather than manually manipulating hardware.

NAVER DAN 2025 Report

contact@hyperaccel.ai (HyperAccel) — Fri, 05 Dec 2025 13:22:41 +0900

NAVER DAN 2025 Report

Introduction

Hello! I’m Sinhyun Park from the HyperAccel ML team. I’d like to share my thoughts after attending NAVER DAN 2025, held at COEX on November 6-7, 2025.

Motivation for Attending

The main objectives for attending this conference were:

Gaining insights on scalable storage infrastructure: Beyond sharing data between nodes within a computing cluster, I wanted to acquire technical insights for building storage infrastructure that enables data exchange across different clusters.

SGLang paper review

contact@hyperaccel.ai (HyperAccel) — Sat, 29 Nov 2025 15:10:28 +0900

Philosophy of SGLang

Since the introduction of LLMs, they have been used to solve complex tasks in various fields—including problem-solving, code writing, and answering questions. Today, they are expanding their ability to be agentic, completing tasks users request without human interference.

This requires a wide range of prompting techniques, such as skeleton of thought or tree of thought. In other words, we structure LLMs to follow certain patterns to fit our needs, and we require programmability to control and guide them to meet our requirements.

[Crafting Compilers - Part 01] Series Introduction

contact@hyperaccel.ai (HyperAccel) — Sun, 16 Nov 2025 15:10:28 +0900

Compilers

This will be a series of posts describing what compilers are, how they are crafted, and how to build your own compiler. Compilers are complicated (sort of) programs that translate high-level programs (written in English mostly) into binary formats that computers can understand. Engineering compilers means designing the way that programs are translated.

Let’s first think about what “programs” are, and how they look. I would define a program as a sequence of instructions for hardware to execute. So at the base level, programs are just sets of instructions composed of “1"s and “0"s. One of the original forms of programs was the assembly language used for computers such as the IBM 360. Programmers in the old days wrote hardware instructions directly to make computers run mission-critical programs such as calculating the trajectory of space rockets or managing bank accounts. These directly expressed what the computer should do at each step, and programmers had to be aware of all the hardware details the computer had. They had to manually calculate register usage, memory state, and every hardware detail, or their program would malfunction and blow up their spaceships.

Pytorchcon2025 Report

contact@hyperaccel.ai (HyperAccel) — Mon, 10 Nov 2025 09:38:03 +0900

PyTorch Conference 2025 Report

Introduction

Hello, I’m Minho Park, Lead of the ML Team at HyperAccel. I attended the PyTorch Conference 2025 held in San Francisco on October 22-23, and I’d like to share my observations and insights.

About HyperAccel

HyperAccel is a company that designs AI chips for efficient inference of Large Language Models (LLMs). We have completed IP verification with FPGA, and our ASIC chip and server are scheduled for release next year. For ASIC, we plan to provide an SDK that supports PyTorch for inference, along with vLLM and Kubernetes support.