LLM & Models
Project Glasswing: Claude Mythos Preview
Centered on Anthropic’s Project Glasswing and Claude Mythos Preview, this post explains why cybersecurity …
HYPERACCEL TECH BLOG
From transistors to LLM inference,
we write about full-stack AI.
Chip design, memory, compilers, infrastructure, and models. HyperAccel engineers write down what they learn across every layer of the AI stack.
Click a layer to unfold its posts below
L5 · Model
LLM & Models
Transformer internals, serving frameworks, and analyses of recent models.
LLM & Models
Transformer World: A Deep Dive into the Building Blocks of LLMs
A hands-on walkthrough of Transformer-based LLM internals — from each module’s role to key optimization …
LLM & Models
SGLang paper review
Philosophy of SGLang Since the introduction of LLMs, they have been used to solve complex tasks in various …
L4 · Infra
Infra & DevOps
How HyperAccel builds its infrastructure: Kubernetes dev environments, CI/CD, device plugins.
Infra & DevOpsK8s Dev Environment - Part 03
Kubernetes Device Plugin for LPU
Hello! I’m Younghoon Jun, a DevOps Engineer on the ML team at HyperAccel. This post is the third installment …
Infra & DevOpsK8s Dev Environment - Part 02
CI/CD Infrastructure Modernization with ARC
The complete journey of redesigning HyperAccel’s CI/CD infrastructure based on Actions Runner Controller …
Infra & DevOpsK8s Dev Environment - Part 01
Why Kubernetes?
Hello! I’m Younghoon Jun, a DevOps Engineer on the ML team at HyperAccel. For those of you reading this, what …
L3 · Compiler
Compilers & Kernels
The software stack above the silicon: compiler theory, torch.compile, custom kernels, and Legato.
Compilers & KernelsExploring torch.compile() - Part 03
Three Keywords from PyTorch Conference 2026: Agent, Acceleration, Ecosystem
Where the industry is heading, as seen at PyTorch Conference 2026, through three keywords: Agent, …
Compilers & KernelsExploring torch.compile() - Part 02
Why Split It into Three Stages?
Why is torch.compile split into Dynamo, AOTAutograd, and Inductor? Starting from how PyTorch grew its …
Compilers & KernelsMonads and Category Theory - Part 01
When Functions Do Not Compose
Starting with a type mismatch between functions that return Option, we explore how branching, map, join, and …
Compilers & KernelsExploring torch.compile() - Part 01
The Three Components
We take torch.compile apart into its three components — TorchDynamo, AOTAutograd, and TorchInductor — and walk …
Compilers & KernelsLegato - Part 01
A Programming Language for HyperAccel LPU
An introduction to Legato — HyperAccel’s programming model and compiler stack for the LPU — covering what it …
Compilers & Kernels
AITER Analysis: How AMD Doubled ROCm Inference Performance
An analysis of AITER (AI Tensor Engine for ROCm), which boosts inference performance on AMD GPUs.
Compilers & KernelsKnow Your Enemy - Extra
Pallas Programming Model
Learn about Pallas programming model that enables writing custom kernels on TPU.
Compilers & KernelsCrafting Compilers - Part 03
Polyhedral Analysis
Today I brought a somewhat different topic. Have you ever thought it would be great if a compiler could …
Compilers & KernelsCrafting Compilers - Part 02
Building a Programming Language
Before building a compiler, we need to define the language it will compile. A programming language isn’t just …
Compilers & KernelsCrafting Compilers - Part 01
Series Introduction
Compilers This will be a series of posts describing what compilers are, how they are crafted, and how to build …
L2 · Memory
Memory & Storage
The memory hierarchy of the AI era: HBM, HBF, CXL, and KV-cache storage tiers.
Memory & StorageCeph Deep-Dive - Part 01
CRUSH
A walkthrough of CRUSH, the data distribution algorithm at the heart of Ceph, based on the SC'06 paper. It …
Memory & StorageMemory in the AI Era - Part 05
Exploring CXL Workloads
We examine how CXL is used in real workloads through KV cache offload, memory pooling, and memory tiering.
Memory & StorageMemory in the AI Era - Part 04
Understanding CXL
Next to the GPU, HBM and HBF fill the gap — but there’s another empty seat next to the CPU. We look at CXL, …
Memory & StorageMemory in the AI Era - Part 03
The Remaining Challenges of HBF
HBF clearly has its place, but it still has gaps to fill before it can claim a spot in the memory hierarchy …
Memory & StorageMemory in the AI Era - Part 02
Where Does HBF Actually Fit?
Centered on SK hynix’s H³ architecture, we explore workloads that can overcome HBF’s weaknesses.
Memory & StorageMemory in the AI Era - Part 01
Understanding HBF
Why are there so many types of memory, and where does HBF fit in? From SRAM to HBF, we explore the physical …
Memory & StorageKnow Your Enemy - Part 04
Memory Capacity Bottleneck and NVIDIA ICMS
We explore the technical principles behind NVIDIA’s ICMS — a new storage tier designed to solve the KV cache …
L1 · Hardware
AI Hardware
Architecture deep dives on AI accelerators: GPU, TPU, LPU, wafer-scale chips, and CPUs.
AI Hardware
Verifying an LLM Inference Chip, Part 1: Where Does the Ground Truth Come From?
When the same AI model gives different answers on a GPU and on the LPU’s RTL, who is wrong? This post covers …
AI HardwareKnow Your Enemy - Part 07
A Model Trained on GPUs Builds a Better Chip Than GPUs
The era of using AI to build chips that run AI has arrived. Drawing on publicly released information about …
AI HardwareKnow Your Enemy - Part 06
The Agentic AI Era — The Revival of the CPU and the Dawn of the CPU Three Kingdoms
We analyze why the CPU became the bottleneck of inference infrastructure in Agentic AI workloads, walk through …
AI HardwareKnow Your Enemy - Part 05
Cerebras and the Wafer-Scale Engine
This post explains Cerebras’s recent momentum, WSE-3 architecture, and the trade-offs of wafer-scale chips in …
AI HardwareKnow Your Enemy - Part 03
Groq's LPU (Acquired by NVIDIA for $20B)
We explore the background of Groq and LPU, their hardware/software design philosophy, and analyze NVIDIA’s …
AI HardwareKnow Your Enemy - Part 02
TPU Emergence and Rise
We explore the background of TPU’s emergence and analyze Google’s AI semiconductor strategy by examining its …
AI HardwareKnow Your Enemy - Part 01
GPU History and Fundamentals
An overview of how NVIDIA GPUs evolved and how the Hopper architecture hides memory latency with massive …
작성 중인 글
Latest
All 38 posts →Compilers & KernelsExploring torch.compile() - Part 03
Three Keywords from PyTorch Conference 2026: Agent, Acceleration, Ecosystem
Where the industry is heading, as seen at PyTorch Conference 2026, through three keywords: Agent, …
Memory & StorageCeph Deep-Dive - Part 01
CRUSH
A walkthrough of CRUSH, the data distribution algorithm at the heart of Ceph, based on the SC'06 paper. It …
AI Hardware
Verifying an LLM Inference Chip, Part 1: Where Does the Ground Truth Come From?
When the same AI model gives different answers on a GPU and on the LPU’s RTL, who is wrong? This post covers …
Series
1 parts
Torch.compile() 알아보기
Where the industry is heading, as seen at PyTorch Conference 2026, through three keywords: Agent, …
1 parts
Ceph Deep-Dive
A walkthrough of CRUSH, the data distribution algorithm at the heart of Ceph, based on the SC'06 …
1 parts
Verifying an LLM Inference Chip
When the same AI model gives different answers on a GPU and on the LPU’s RTL, who is wrong? This …
2 parts
Monads and Category Theory Starting From Code
Starting with a type mismatch between functions that return Option, we explore how branching, map, …
2 parts
Exploring Torch.compile()
We take torch.compile apart into its three components — TorchDynamo, AOTAutograd, and TorchInductor …
8 parts
Know Your Enemy, Know Yourself
An overview of how NVIDIA GPUs evolved and how the Hopper architecture hides memory latency with …
5 parts
Memory in the AI Era
Why are there so many types of memory, and where does HBF fit in? From SRAM to HBF, we explore the …
1 parts
Legato
An introduction to Legato — HyperAccel’s programming model and compiler stack for the LPU — covering …
2 parts
AI Agent Series
Hello, my name is Taeseo Um, currently on the ML team at HyperAccel. There is a running joke among …
3 parts
Building an In-House Dev Environment on Kubernetes
Hello! I’m Younghoon Jun, a DevOps Engineer on the ML team at HyperAccel. For those of you reading …
3 parts
Crafting Compilers
Compilers This will be a series of posts describing what compilers are, how they are crafted, and …
AI Hardware
Architecture deep dives on AI accelerators: GPU, TPU, LPU, wafer-scale chips, and CPUs.
AI Hardware
Verifying an LLM Inference Chip, Part 1: Where Does the Ground Truth Come From?
AI HardwareKnow Your Enemy - Part 07
A Model Trained on GPUs Builds a Better Chip Than GPUs
AI HardwareKnow Your Enemy - Part 06
The Agentic AI Era — The Revival of the CPU and the Dawn of the CPU Three Kingdoms
AI HardwareKnow Your Enemy - Part 05
Cerebras and the Wafer-Scale Engine
AI HardwareKnow Your Enemy - Part 03
Groq's LPU (Acquired by NVIDIA for $20B)
AI HardwareKnow Your Enemy - Part 02
TPU Emergence and Rise
AI HardwareKnow Your Enemy - Part 01
GPU History and Fundamentals
Memory & Storage
The memory hierarchy of the AI era: HBM, HBF, CXL, and KV-cache storage tiers.
Memory & StorageCeph Deep-Dive - Part 01
CRUSH
Memory & StorageMemory in the AI Era - Part 05
Exploring CXL Workloads
Memory & StorageMemory in the AI Era - Part 04
Understanding CXL
Memory & StorageMemory in the AI Era - Part 03
The Remaining Challenges of HBF
Memory & StorageMemory in the AI Era - Part 02
Where Does HBF Actually Fit?
Memory & StorageMemory in the AI Era - Part 01
Understanding HBF
Memory & StorageKnow Your Enemy - Part 04
Memory Capacity Bottleneck and NVIDIA ICMS
Compilers & Kernels
The software stack above the silicon: compiler theory, torch.compile, custom kernels, and Legato.
Compilers & KernelsExploring torch.compile() - Part 03
Three Keywords from PyTorch Conference 2026: Agent, Acceleration, Ecosystem
Compilers & KernelsExploring torch.compile() - Part 02
Why Split It into Three Stages?
Compilers & KernelsMonads and Category Theory - Part 01
When Functions Do Not Compose
Compilers & KernelsExploring torch.compile() - Part 01
The Three Components
Compilers & KernelsLegato - Part 01
A Programming Language for HyperAccel LPU
Compilers & Kernels
AITER Analysis: How AMD Doubled ROCm Inference Performance
Compilers & KernelsKnow Your Enemy - Extra
Pallas Programming Model
Compilers & KernelsCrafting Compilers - Part 03
Polyhedral Analysis
Compilers & KernelsCrafting Compilers - Part 02
Building a Programming Language
Compilers & KernelsCrafting Compilers - Part 01
Series Introduction
LLM & Models
Transformer internals, serving frameworks, and analyses of recent models.
LLM & Models
Project Glasswing: Claude Mythos Preview
LLM & Models
Transformer World: A Deep Dive into the Building Blocks of LLMs
LLM & Models
SGLang paper review
Infra & DevOps
How HyperAccel builds its infrastructure: Kubernetes dev environments, CI/CD, device plugins.
Infra & DevOpsK8s Dev Environment - Part 03
Kubernetes Device Plugin for LPU
Infra & DevOpsK8s Dev Environment - Part 02
CI/CD Infrastructure Modernization with ARC
Infra & DevOpsK8s Dev Environment - Part 01
Why Kubernetes?
Engineering Culture
How we work: AI coding agents, development methodologies, and running this tech blog.
Engineering CultureAI Agent - Part 02
Back to the Terminal: How Agents Made Remote Development Feel Native
Engineering CultureAI Agent - Part 01
From Copy-Paste to Autonomous Agents: A Subtle Introduction
Engineering Culture
Specs are All You Need: What is Spec-Driven Development (SDD)?
Engineering Culture
Starting Our Tech Blog
Conference Reports
Field reports from CES, NAVER DAN, PyTorch Conference, and more.
Conference Reports
CES 2026 Key Highlights from a 2025 Participant (feat. SAMSUNG, SK, LG)
Conference Reports
NAVER DAN 2025 Report
Conference Reports
Pytorchcon2025 Report
Semiconductor
Programming Language
Programming Language