HyperAccel is excited to announce that our latest AI chip, Adelia, was presented at the prestigious VLSI Symposium 2025 held in June in Kyoto, Japan. The presentation was delivered by Jung-Hoon Kim, a Ph.D. candidate at KAIST, highlighting our continued commitment to advanced semiconductor innovation and high-performance AI computing.
📄 Paper Title
Adelia: A 4nm LLM Accelerator with Streamlined Dataflow and Dual-Mode Parallelization for Efficient Generative AI Inference
💻 Technical Summary
Adelia is a cutting-edge 4nm inference accelerator purpose-built for large language models (LLMs). It features:
- A streamlined dataflow architecture
- Dual-mode parallelization that dynamically balances latency and throughput
- A compact 5.28 mm² die design
With these innovations, Adelia achieves up to 91% memory bandwidth utilization and delivers performance that significantly surpasses the H100 GPU in both bandwidth and throughput efficiency—marking a major milestone in efficient and scalable generative AI acceleration.
📢 What’s Next
Our next presentation will take place at ISCA 2025 (June 21–25, Tokyo, Japan).
More exciting advancements are ahead—stay tuned!